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bluespec-systemverilog-language

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Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

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Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.

processor-architecture ram hardware processor bus bluespec hardware-designs vlsi hardware-acceleration vlsi-physical-design bluespec-systemverilog processor-design vector-processor vlsi-design bluespec-systemverilog-language vlsi-cad
  • Updated Jan 11, 2021
  • Bluespec

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