DUT-Verification-and-Testing-Using-System-Verilog

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Verification Methodology

The testbench follows a layered verification approach inspired by UVM concepts:

1. Transaction generation → 2. Driver stimulation → 3. Monitoring & Coverage collection → 4. Scoreboarding for validation.

All tests are self-checking, ensuring automated result validation without manual intervention.

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File Structure

   
├── demux_logic.sv
├── testbench_1.sv
├── interface.sv
├── packet.sv
├── covergroup.sv
├── monitor.sv
├── driver.sv
├── queue.sv
├── scoreboard.sv
├── testbench_2.sv
└── README.md   

Implementation Steps

1. Designed 1-bit slice and 4-bit DUT modules.
2. Created simple testbench for functional validation.
3. Implemented SystemVerilog interface for DUT connectivity.
4. Developed randomized packet generation (50 transactions).
5. Implemented self-checking testbench with driver, monitor, and scoreboard.
6. Collected coverage metrics to ensure verification completeness.

Testbench Architecture

The verification environment includes:

• Interface: Defines input and output connections between DUT and Testbench.
• Driver: Sends randomized stimulus to DUT.
• Monitor: Captures DUT outputs for analysis.
• Packet Class: Generates random transactions (a, b, c, d, sel).
• Scoreboard: Compares DUT output with expected results.
• Coverage Group: Tracks functional coverage for all input combinations and cross coverage (sel x a, sel x b, sel x c).

Simulation & Tools

• Language: SystemVerilog (IEEE 1800-2017)
• Simulator: ModelSim
• Target Design: 4-bit logic (e.g., demultiplexer)
• Verification Method: Coverage-driven, randomized testing

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Results

• Achieved complete functional coverage.
• Successfully verified DUT functionality across all 4-bit combinations.
• Demonstrated efficient, modular, and reusable verification environment.

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Author

Marisa Mathew MTech in (VLSI & Embedded Systems)
Developed as part of a SystemVerilog verification project using interface-based and coverage-driven techniques.

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License

This repository is protected under All Rights Reserved © 2025 Marisa Mathew